With the increasing down-scaling of semiconductor devices, various processing techniques, such as, photolithography are adapted to allow for the manufacture of devices with increasingly smaller dimensions. However, as semiconductor processes require smaller process windows, the manufacture of these devices have approached and even surpassed the theoretical limits of photolithography equipment. As semiconductor devices continue to shrink, the spacing desired between elements (i.e., the pitch) of a device is less than the pitch that can be manufactured using traditional optical masks and photolithography equipment.
One approach used to achieve the higher resolutions to manufacture smaller devices is to use multiple pattern lithography. For example, a half pitch (i.e., half of the minimum photolithographic pitch achievable in a traditional photolithography system) can be achieved by forming mandrels (e.g., at a minimum available pitch), conformably forming a sidewall aligned spacer over the mandrels, anisotropically etching top portions of the spacer to expose the mandrels, removing the mandrels while leaving the spacer, and then using the spacer as a patterning mask to transfer the desired pattern to underlying layers. In this manner, line spacing at approximately half the minimum pitch can be achieved.
An issue with this approach is the anisotropic etching of the spacer may create spacer footing due to process limitations for uniform etching. That is, bottom portions of spacer may not be substantially perpendicular to underlying layers and may include a large fillet that extends excessively outwards in a horizontal direction. Spacer footing creates reliability issues for using the spacer as a mask to transfer a desired pattern to the underlying layer.